New Directions in Computer Architecture

2nd Workshop on
New Directions in Computer Architecture (NDCA-2)

Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38)
San Jose, California, Sunday June 5th, 08:25-12:05

Workshop Summary
The last few years have witnessed a dramatic shift of focus toward multi-core systems in both the microprocessor industry and the architecture research community. Due in large part to power and complexity limitations to single-core scaling, multi-core architectures have emerged as the primary mechanism to reap the benefits of Moore's Law in the billion-transistor era. However, the challenge of making parallelization an easy task for most programmers, combined with worsening power constraints, may jeopardize the notion of many-cores. Extreme process variations and the increasing number of transient and permanent faults will further complicate the design of traditional computing systems. And increasingly, the slowing of CMOS process scaling calls for alternative computing or technology paths. In addition to these design challenges, the shift towards data centers and mobile computing is likely to change the requirements for traditional architectures radically. The goal of the New Directions in Computer Architecture workshop is to bring together top researchers in the community for presentations and discussions about what the future of the technology is likely to hold, and in what new areas the research community should be investing.

Program

08:25-08:30	Introduction
08:30-09:30	Keynote: What to Do About the End of Moore's Law (Probably) ?	Lakshmi N. B. Chakrapani (Google)
09:30-09:50	10x10: Taming Heterogeneity for General-purpose Architecture	Andrew A. Chien (UCSD)
09:50-10:10	Trustworthy from the Silicon Up	Tim Sherwood (UCSB)
10:10-10:25	Break
10:25-10:45	Object Oriented execution Model (OOM)	Nikola Markovic, Daniel Nemirovsky, Osman Unsal, Mateo Valero, Adrian Cristal (BSC, Barcelona, Spain)
10:45-11:05	Stories, not Words: Abstract Datatype Processors	Martha Kim (Columbia University)
11:05-11:25	Pattern Learning to Enhance Task and Data Management Efficiency	Junli Gu (Tsinghua University, Beijing, China & UIUC), Steven S. Lumetta, Sanjay J. Patel (UIUC), Yihe Sun (Tsinghua University, Beijing, China)
11:25-11:45	Memory Contexts: Supporting Selectable Cache and TLB Contexts	Tim Brecht (University of Waterloo, Canada)
11:45-12:05	On Memory Relaxations for Extreme Manycore System Scalability	Holger Froning (University of Heidelberg, Mannheim, Germany), Hector Montaner, Federico Silla, Jose Duato (UPV, Valencia, Spain)

For the final version, authors can either keep their 1-page abstract or submit a longer paper (1 to 4 pages; longer papers can be accommodated).

1 to 2 papers will be selected for publication in IEEE CAL (4-page format).